Algebraic Models of Temporal Abstraction for Initialised Iterated State Systems: An Abstract Pipelined Case Study

The data and temporal abstractions of a pipelined case study are explored in an algebraic setting. We apply a set of algebraic tools for modelling microprocessors to the specification, pipelined implementation, and formal verification of an abstract case study. We employ a model of time based on counting events by means of a clock. We model systems as iterated maps that evolve over time from some initial state. We define formal correctness conditions, and introduce the one-step theorems that, given certain conditions, reduce the complexity of formal verification. The algebraic models provide: (i) modular descriptions of pipelined systems, including correctness criteria; and (ii) equational specification and verification techniques for the design of pipelined systems applicable to a range of specification languages and theorem provers.